The present invention relates to a vector processing apparatus having scalar and vector processors.
A prior art vector processor uses a scalar instruction for scalar processing and a vector instruction for vector processing. There are two methods to execute those two instructions.
In a first method, one logical unit decodes a hybrid system of the scalar instruction and the vector instruction. In this method, it is easy for a user to understand the programming structure of a program described by the scalar and vector instructions. In this method, floating point and fixed point registers can be shared by the scalar and vector processors so that data is exchanged between the processors at the register level. By sharing the registers, a scalar event directly interacts with the vectors and vice versa. From the standpoint of software, such as a compiler, depending on the order of access to the common registers, the scalar and vector instructions can be executed.
In a second method, the scalar instructions and the vector instructions are classified into two blocks, and the vector instructions in the block are sub-divided in the order of execution. The vector processor executes the sub-divided vector instructions. A logical combination of the vector instruction groups is designated by a vector processor start-up instruction, a set-up instruction or a vector processor status test instruction. In this method, the scalar instruction is decoded by a scalar processor and the vector instruction is decoded by a vector processor. This method has a higher freedom in parallel processing than the first method, and it is effective to attain a higher degree of parallel calculation. The second method is introduced by an article "Hitachi Supercomputer S-810 Array Processor System" by T. Odaka et al, "SUPERCOMPUTERS", Elesevier Science Publishers B. V., 1986.
In the second method, since the data is simultaneously processed by the scalar and vector processors, common registers cannot be used by the processors and the execution control between the processors by register numbers is not performed. From the standpoint of software which assumes conventional serial execution control, it makes debugging (logical validation) of code difficult. Further, unless sufficient communication means for status between the processors is provided, synchronous defects frequently occur when a serially structured algorithm is copied into parallel codes, and an expected performance is not attained. This means that processor synchronization control is particularly important when parallel hardware means are constructed to attain a high-speed vector processing.